Instruction Fetch Address Register

Instruction Fetch Address Register
Information technology: IFAR (Power4, IBM, CPU)

Универсальный русско-английский словарь. . 2011.

Игры ⚽ Поможем написать реферат

Смотреть что такое "Instruction Fetch Address Register" в других словарях:

  • Instruction cycle — An instruction cycle (sometimes called fetch and execute cycle, fetch decode execute cycle, or FDX) is the basic operation cycle of a computer. It is the process by which a computer retrieves a program instruction from its memory, determines what …   Wikipedia

  • Register machine — In mathematical logic and theoretical computer science a register machine is a generic class of abstract machines used in a manner similar to a Turing machine. All the models are Turing equivalent. Contents 1 Overview 2 Formal definition 3 …   Wikipedia

  • Instruction set simulator — An instruction set simulator (ISS) is a simulation model, usually coded in a high level programming language, which mimics the behavior of a mainframe or microprocessor by reading instructions and maintaining internal variables which represent… …   Wikipedia

  • Instruction set — An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception… …   Wikipedia

  • Cycles per instruction — In computer architecture, cycles per instruction (aka clock cycles per instruction, clocks per instruction, or CPI) is a term used to describe one aspect of a processor s performance: the number of clock cycles that happen when an instruction is… …   Wikipedia

  • Burroughs large systems instruction set — The B5000 instruction set is the set of valid operations for the Burroughs large systems including the current (as of 2006) Unisys Clearpath/MCP systems. These unique machines have a distinctive design and instruction set. Each word of data is… …   Wikipedia

  • Explicitly Parallel Instruction Computing — EPIC bezeichnet eine Eigenschaft einer Befehlssatzarchitektur (englisch Instruction Set Architecture, kurz ISA) und der Verarbeitungsstruktur einer Familie von Mikroprozessoren, z. B. Itanium. Bei der Programmierung von EPIC CPUs wird… …   Deutsch Wikipedia

  • IFAR — abbr. Instruction Fetch Address Register (Power4, IBM, CPU) …   United dictionary of abbreviations and acronyms

  • Classic RISC pipeline — In the history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar architectural solution, now called a classic RISC pipeline. Those CPUs were: MIPS, SPARC, Motorola 88000,… …   Wikipedia

  • CPU cache — Cache memory redirects here. For the general use, see cache. A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the… …   Wikipedia

  • Microcode — is a layer of hardware level instructions and/or data structures involved in the implementation of higher level machine code instructions in many computers and other processors; it resides in special high speed memory and translates machine… …   Wikipedia


Поделиться ссылкой на выделенное

Прямая ссылка:
Нажмите правой клавишей мыши и выберите «Копировать ссылку»